1. Field
The present application relates to a liquid crystal display (LCD) device, and a shift register and an LCD device using the same, in which synchronization between a start pulse and a clock signal is unnecessary.
2. Discussion of the Related Art
Demand for various display devices has increased with development of an information society. Accordingly, much effort have been expended to research and develop various flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some species of flat display devices have already been applied to displays of various equipment.
Among the various flat display devices, liquid crystal display (LCD) devices have been most widely used due to advantageous characteristics of thin profile, lightness in weight, and low power consumption, whereby the LCD devices provide a substitute for a Cathode Ray Tube (CRT). In addition to mobile type LCD devices such as a display for a notebook computer, LCD devices have been developed for computer monitors and televisions to receive and display broadcast signals.
Despite various technical developments in the LCD technology with applications in different fields, research in enhancing the picture quality of the LCD device has been in some respects lacking as compared to other features and advantages of the LCD device. Therefore, in order to use the LCD device in various fields as a general display, the key to developing the LCD device lies on whether the LCD device can implement a high quality picture, such as high resolution and high luminance with a large-sized screen while still maintaining lightness in weight, thinness, and low power consumption.
In general, the LCD device includes an LCD panel for displaying an image and a driver for supplying a driving signal to the LCD panel. In addition, the LCD panel includes first and second glass substrates bonded to each other having a cell gap therebetween, and a liquid crystal layer formed between the first and second glass substrates.
The first glass substrate (TFT array substrate) includes a plurality of gate lines arranged along a first direction at fixed intervals, a plurality of data lines arranged along a second direction perpendicular to the first direction at fixed intervals, a plurality of pixel electrodes arranged in a matrix-type configuration within pixel regions defined by crossing of the gate and data lines, and a plurality of thin film transistors enabled according to signals supplied to the gate lines for transmitting signals from the data lines to the pixel electrodes.
Also, the second glass substrate (color filter array substrate) includes a black matrix layer that prevents light from portions of the first substrate other than the pixel regions, an R/G/B color filter layer for displaying various colors, and a common electrode for producing the image. The cell gap is maintained between the first and second substrates by spacers, and then the first and second substrates are bonded together by a sealant.
Hereinafter, a driving circuit of a related art LCD device will be described as follows. FIG. 1 is a block diagram of a driving circuit of a related art LCD device. As shown in FIG. 1, a related art LCD device includes an LCD panel 21 having a plurality of gate and data lines G and D crossing each other to define a plurality of pixel regions arranged in a matrix-type configuration, a driving circuit 22 for providing a scanning signal and a data signal to the LCD panel 21, and a backlight 28 for providing a uniform light source to the LCD panel 21.
The driving circuit 22 includes a data driver 21b, a gate driver 21a, a timing controller 23, a power supply unit 24, a gamma reference voltage unit 25, a DC/DC converter 26, and an inverter 29. The data driver 21b inputs a data signal to each data line D of the LCD panel 21, and the gate driver 21a supplies a scanning signal to each gate line G of the LCD panel 21. Then, the timing controller 23 receives display data R/G/B, vertical and horizontal synchronous signals Vsync and Hsync, a clock signal DCLK and a control signal DTEN from a driving system 27 of the LCD panel 21, and formats the display data, the clock signal and the control signal at a timing suitable for restoring a picture image by the gate driver 21a and the data driver 21b of the LCD panel 21. The power supply unit 24 supplies a voltage to the LCD panel 21 and respective units. Also, the gamma reference voltage unit 25 receives power from the power supply unit 24 to provide a reference voltage required when digital data inputted from the data driver 21b is converted to analog data. The DC/DC converter 26 outputs a constant voltage VDD, a gate high voltage VGH, a gate low voltage VGL, a reference voltage Vref, and a common voltage Vcom for the LCD panel 21 by using a voltage outputted from the power supply unit 24. Also, the inverter 29 drives the backlight 28.
An operation of the driving circuit of the related art LCD device will be described as follows. That is, the timing controller 23 receives the display data R/G/B, the vertical and horizontal synchronous signals Vsync and Hsync, the clock signal DCLK, and the control signal DTEN from the driving system 27 of the LCD panel, and provides the display data, the clock signal, and control signal at the timing suitable for restoring the picture image by the gate driver 21a and the data driver 21b of the LCD panel 21. Thus, the gate driver 21a supplies the scanning signal to each gate line G of the LCD panel 21, whereby the data driver 21b supplies the data signal to each data line D of the LCD panel 21, thereby displaying the inputted image signal. The gate driver includes a shift register for sequentially providing the scanning signal to each gate line.
Hereinafter, a related art shift register will be described with reference to the accompanying drawings. FIG. 2 is a schematic view of a related art shift register. FIG. 3 is a circuit diagram for each stage of FIG. 2. As shown in FIG. 2, the related art shift register includes a plurality of stages (51a, 51b, 51c, 51d, . . . , 51n) for receiving clock signals CLKA and CLKB, and supply voltages VDD and VSS to synchronously output gate driving pulses for driving respective gate lines G in sequence.
The first stage 51a receives a start pulse SP, the first clock signal CLKA, the second clock signal CLKB, the first supply voltage VDD, and the second supply voltage VSS, and then outputs the first gate driving pulse Vout1. The second stage 51b receives the first gate driving pulse Vout1 of the first stage 51a, the first clock signal CLKA, the second clock signal CLKB, the first supply voltage VDD, and the second supply voltage VSS, and then outputs the second gate driving pulse Vout2, wherein the second gate driving pulse Vout2 is delayed by one period from the first gate driving pulse Vout1. The n-th stage 51n receives the (n−1)th gate driving pulse Voutn−1 of the (n−1)th stage 51n−1, the first clock signal CLKA, the second clock signal CLKB, the first supply voltage VDD, and the second supply voltage VSS, and then outputs the n-th gate driving pulse Voutn, wherein the n-th gate driving pulse Voutn is delayed by one period from the (n−1)th gate driving pulse Voutn−1.
In brief, only the first stage 51a receives the start pulse SP. Meanwhile, the remaining of the stages, from the second stage to the n-th stage 51b to 51n respectively, use the output driving pulse (Vout1 to Voutn−1) of the prior stage, so that the remaining stages output a gate driving pulse (Vout2 to Voutn) that is delayed by one period from the prior output diving pulse (Vout1 to Voutn−1). Accordingly, the gate driving pulses (Vout1 to Voutn) outputted from the respective stages (51a, 51b, 51c, 51d, . . . , 51n) are provided to the respective gate lines G, thereby scanning the gate lines G in sequence.
For this, each of the stages (51a, 51b, 51c, 51d, . . . , 51n) has a circuit shown in FIG. 3. The circuit for each stage (51a, 51b, 51c, 51d, . . . , 51n) has the same structure. However, the first and second clock signals CLKA and CLKB are alternately applied to the odd numbered stages (51a, 51c, 51e, . . . ), and the even numbered stages (51b, 51d, . . . ). Herein, the circuit for the first stage 51a will be explained as follows.
That is, as shown in FIG. 3, the first stage 51a further includes a first PMOS transistor T1, a second PMOS transistor T2, a third PMOS transistor T3, a fourth PMOS transistor T4, a fifth PMOS transistor T5, and a sixth PMOS transistor T6. The first PMOS transistor T1 is turned-on/off by logic of the first clock signal CLKA, and the first PMOS transistor T1 provides the start pulse SP to a first node P1 when in the turned-on state. Also, the second PMOS transistor T2 is turned-on/off by logic of the first clock signal CLKA, and the second PMOS transistor T2 provides the first supply voltage VDD to a second node P2 when in the turned-on state. The third PMOS transistor T3 is turned-on/off by logic of the start pulse SP charged in the first node P1, and the third PMOS transistor T3 provides the second clock signal CLKB to an output line 50a when in the turned-on state. The fourth PMOS transistor T4 is turned-on/off dependent on the state of the second node P2, and the fourth PMOS transistor T4 provides the second supply voltage VSS to the output line 50a when in the turned-on state. The fifth PMOS transistor T5 is turned-on/off by logic of the start pulse SP charged in the first node P1, and the fifth PMOS transistor T5 passes the second supply voltage VSS when in the turned-on state. The sixth PMOS transistor T6 is turned-on/off by logic of the second clock signal CLKB, and the sixth PMOS transistor T6 charges the second node P2 with the second supply voltage VSS passing through the fifth PMOS transistor T5 when in the turned-on state.
In this case, the second node P2 may be charged with the first supply voltage VDD or the second supply voltage VSS. If the second node P2 is charged with the first supply voltage VDD of low logic, the fourth PMOS transistor T4 connected with the second node P2 is turned-on. If the second node P2 is charged with the second supply voltage VSS of high logic, the fourth PMOS transistor T4 is turned-off.
Meanwhile, the second clock signal CLKB provided to the output line 50a of the first stage 51a through the third PMOS transistor T3 or the fourth PMOS transistor T4 is used for the first gate driving pulse Vout1, and also is used for the start pulse SP of the next stage 51b. 
As described above, for the odd numbered stages (51a, 51c, 51e, . . . ), the first clock signal CLKA is applied to gate terminals of the first PMOS transistor T1 and the second PMOS transistor T2, and the second clock signal CLKB is applied to a source terminal of the third PMOS transistor T3. For the even numbered stages (51b, 51d, . . . ), the second clock signal CLKB is applied to the gate terminals of first PMOS transistor T1 and the second PMOS transistor T2, and the first clock signal CLKA is applied to the source terminal of the third PMOS transistor T3.
An operation of the shift register will be described as follows. FIG. 4 is a timing view for each signal provided to a related art shift register.
First, an operation of the shift register during a first period (A) will be described in detail. That is, as shown in FIG. 4, during the first period (A), the start pulse SP and the first clock signal CLKA are maintained in the low logic state, and the second clock signal CLKB is maintained in the high logic state. The first clock signal CLKA of the low logic state is applied to the gates of the first PMOS transistor T1 and the second PMOS transistor T2.
Then, the first PMOS transistor T1 and the second PMOS transistor T2 are turned-on by the first clock signal CLKA of the low logic state. Thus, the start pulse SP of the low logic state, applied to the source of the first PMOS transistor T1, is provided to the first node P1 through the first PMOS transistor T1, and the first supply voltage VDD of the low logic state, applied to the source of the second PMOS transistor T2, is provided to the second node P2 through the second PMOS transistor T2.
After that, the third PMOS transistor T3 and the fifth PMOS transistor T5, connected with the first node P1 by the gate, are turned-on by the start pulse SP of low logic charged in the first node P1. Also, the fourth PMOS transistor T4 is turned-on by the first supply voltage VDD of low logic charged in the second node P2. Accordingly, the second supply voltage VSS of high logic as well as the high logic of the second clock signal CLKB, is provided to the output line 50a through the fourth PMOS transistor T4. The second clock signal CLKB of high logic is also applied to the gate of the sixth PMOS transistor T6, thereby turning-off the sixth PMOS transistor T6.
Next, an operation of the shift register during a second period (B) will be explained as follows. During the second period (B), the start pulse SP and the first clock signal CLKA are changed to the high logic state, so that the second clock signal CLKB is changed to the low logic state. Thus, the first clock signal CLKA of high logic is applied to the first PMOS transistor T1 and the second PMOS transistor T2 through each gate, whereby the first PMOS transistor T1 and the second PMOS transistor are turned-off. That is, the start pulse SP of low logic charged during the first period (A) is maintained in the same state.
Accordingly, the third PMOS transistor T3 and the fifth PMOS transistor T5 are maintained in the turned-on state by the start pulse SP of low logic charged in the first node P1. As described above, during the second period (B), according as the second clock signal CLKB is changed to the low logic state, the sixth PMOS transistor T6 is turned-on, so that the second supply voltage VSS (+V) of high logic is provided to the second node P2 through the fifth PMOS transistor T5 and the sixth PMOS transistor T6. Thus, the fourth PMOS transistor T4 is turned-off by the second supply voltage VSS of high logic charged in the second node P2, so that the second clock signal CLKB of low logic is provided to the output line 50a through the third PMOS transistor T3.
At this time, during the second period (B), the first PMOS transistor T1 and the second PMOS transistor T2 are turned-off, so that the first node P1 is in the floating state. Also, the start pulse SP of the first node P1 is lowered in correspondence with the second clock signal CLKB of low logic provided to the output line 50a by a parasitic capacitance between the gate and drain of the third PMOS transistor T3. Thus, the higher start pulse SP is applied to the gate of the third PMOS transistor T3, so that a threshold voltage of the third PMOS transistor T3 is lowered. That is, the second clock signal CLKB of low logic is provided to the output line 50a without loss.
Next, an operation of the shift register during a third period (C) will be described as follows. During the third period (C), the start pulse SP is maintained in the high logic state, and the first clock signal CLKA is changed to the low logic state, whereby the second clock signal CLKB is changed to the high logic state. Accordingly, the first PMOS transistor T1 and the second PMOS transistor T2 are turned-on again by the first clock signal CLKA of low logic, and the start pulse SP of high logic is provided to the first node P1 through the first PMOS transistor T1 being turned-on. Thus, the first supply voltage VDD (−V) of low logic is provided to the second node P2 through the second PMOS transistor T2.
After that, the third PMOS transistor T3 and the fifth PMOS transistor T5 are turned-off by the start pulse SP of high logic charged in the first node P1, and the fourth PMOS transistor T4 is turned-on by the first supply voltage VDD of low logic charged in the second node P2. Also, the second clock signal CLKB of high logic is applied to the gate of the sixth PMOS transistor T6, thereby turning-off the sixth PMOS transistor T6. Accordingly, the second supply voltage VSS of high logic is applied to the output line 50a through the fourth PMOS transistor T4.
In this case, the second clock signal CLKB of low logic provided to the output line 50a of the first stage 51a during the second period (B) corresponds to the first gate driving pulse Vout1 for driving the gate line G. Simultaneously, the first gate driving pulse Vout1 outputted from the output line 50a of the first stage 51a is applied to the source terminal of the first PMOS transistor T1 of the second stage 51b, and the second clock signal CLKB is applied to the gate terminals of the first PMOS transistor T1 and the second PMOS transistor T2. Accordingly, the first clock signal CLKA is outputted as the second gate driving pulse Vout2 to the output line 50b of the second stage 51b, wherein the first clock signal CLKA of low logic of the second gate driving pulse Vout2 is delayed (shifted) by one period from the first clock signal CLKA of low logic of the first stage 51a. As a result, the first to n-th gate driving pulses (Vout1 to Voutn) are sequentially provided to the gate lines G by the shift register.
Meanwhile, the start pulse SP may be outputted or not dependent on the logic of the first clock signal CLKA, so that the start pulse SP provided to the first stage is outputted in synchronization with the first clock signal CLKA. That is, as explained above, the first clock signal CLKA is provided to the gate of the first PMOS transistor T1, thereby turning-on/off the first PMOS transistor T1. To charge the start pulse SP in the first node P1 during the first period (A), the first PMOS transistor T1 is maintained in the turned-on state for applying the start pulse SP. For this, the first clock signal CLKA provided to the gate of the first PMOS transistor T1 is necessarily maintained in the low logic state during the first period (A). Thus, in order to operate the related art shift register normally, it is necessary to synchronize the first clock signal CLKA with the start pulse SP.